EMI Analyzer: PCB EMI and EMC checks and openEMS simulation

EMI Analyzer

Upload a KiCad board to see its copper, its stackup and a set of geometric EMI and EMC checks: where it radiates, what it conducts out through its cables, and where ESD and fast transients get in. Full-wave analysis of a selected region runs on openEMS, a real field solver, not an approximation.

New board

Project name

A .kicad_pcb, a zipped KiCad project, or a zip of your Gerber output. Gerbers must include the drill file and an IPC-D-356 netlist — they carry no net information on their own, so without one there is no way to tell which copper is which signal.

Board files are stored in DigitalOcean Spaces and processed by an EmbeddedCI worker — what that means.

How the analysis works

Three stages, and only the last one is slow. Nothing here is a rule-of-thumb estimate standing in for a solver.

Ingest. A .kicad_pcb is parsed straight from its s-expression source, so nets, traces, vias, pads and the stackup arrive as they were drawn. Gerbers take a longer route: every copper layer is rasterised, its connected islands labelled, and the IPC-D-356 netlist coordinates dropped onto them to recover which island is which net. Both paths end at one normalised board model, and everything after this point reads only that.
Geometric checks (seconds). Return paths and plane stitching, decoupling, length matching and impedance, and the layout details that make a board radiate. Then the other half of an EMC test: ESD protection at the connectors, shield and chassis grounding, reset lines that a transient can trip, and the power input and switching-regulator layout behind conducted emissions. Every check is in the table below. No solver is involved, which is why these run on any worker and finish while you wait.
Full-wave solve (hours). openEMS, an EC-FDTD solver, over a region of interest you select. The worker meshes the geometry, excites the nets you nominate, and steps the fields through time on a rectilinear grid. Results come back as frequency-domain surface-current maps per layer, a near-field-to-far-field radiation pattern, and S-parameters. Whole-board solves are not offered: a 100 x 80 mm board meshed at 25 um is around 1.9 billion cells, which no amount of hardware makes practical.

The memory and runtime arithmetic behind a solve, and what the results can and cannot tell you, are on the limitations page.

What every board is checked for

18 checks run on every upload, in seconds, from the board geometry and stackup: what the board radiates and conducts out through its cables, and where ESD and fast transients get in. They say where to look. A solve on a selected region, or a near-field scan loaded onto the board, confirms what is actually radiating. Thresholds and which checks run can be set per board in an emi.rules.yaml.

Area	Check	What it looks for
Return path	Reference plane gaps	A trace crossing a break in the plane beneath it; the return current has to detour, and the loop that creates radiates.
	Missing return vias	A signal changing layer with no nearby via joining the two reference planes, so the return current has no path across.
	Plane stitching	Areas where two ground planes overlap with no via joining them within λ/20; between stitching points the planes form a cavity that resonates.
	Edge stitching	Stretches of board edge where a ground plane reaches the outline with no via fence; an unstitched plane edge radiates like a slot antenna.
	Stackup	Signal layers with no adjacent reference plane, and adjacent signal layers with no plane between them to stop broadside coupling.
Power integrity	Decoupling capacitors	IC supply pins far from a capacitor to ground, and decoupling capacitors whose ground pad has no via nearby. The loop through them sets the frequency above which they stop decoupling.
Signal integrity	Via stubs	The unused length of a through via below the layer a signal leaves on, which resonates.
	Length matching	Members of a matched group whose delay differs from their reference by more than the budget. Measured in time, not millimetres: an inner-layer millimetre and an outer-layer one are about 25% apart.
	Impedance	Computed characteristic impedance against a target, and discontinuities along a net where width or reference plane changes.
Radiation	Long nets	A net long enough against the wavelength to couple to free space efficiently.
	Copper near the board edge	Traces or planes close to the edge, where fields are not contained.
	Floating copper	Pour islands connected to nothing, which pick up and re-radiate with no path to ground.
	Crystals and oscillators	Signals routed under a crystal, and crystals close to the board edge or to a connector, where a cable becomes their antenna.
Conducted emissions	Power input filtering	Power entering through a connector with no capacitor near it, so the loads' switching current flows out along the supply cable and a surge meets nothing on the way in.
Conducted emissions	Switching regulator nodes	Switch nodes with more copper or track than the current needs. The node swings the full input voltage in nanoseconds, and its copper couples that into everything nearby.
Immunity	ESD protection at connectors	Lines leaving the board through an edge connector with no clamp on them, clamps placed far from the connector or after the IC they protect, and clamps with no short path to ground.
	Shield and chassis ground	Connector shells and plated mounting holes connected to nothing, and chassis nets with no path to the board's ground, so a discharge to the enclosure has to cross the circuit.
	Reset lines	Reset inputs held only by a pull-up with no filter capacitor, or with the capacitor far from the pin, where a fast transient on the trace resets the board.

Projects