PCB trace length analyzer
Check trace length matching on a KiCad board. Prefer to work inside KiCad? Install it as a plugin.
- Finds DDR, USB, PCIe, Ethernet, MIPI and other differential pairs.
- Measures each net against its target length.
- Shows what to add, what to shorten and what is not routed.
- Can add meanders for youexperimental
- Upload the .kicad_pcb, plus the .kicad_pro and .kicad_dru for your rules.
- Your file is never modified.
- Only you can see the board.
- Deleted after a few hours.
Length
- Ltrack: track centerline, pad to pad
- hvia: via height from the stackup, 0 if
use_height_for_length_calcsis off - Lpad: pad center to track, both ends
- Lpackage: die length, both ends
- Fly-by lines: per leg
Target
- No reference routed: the longest net
- Lone differential pair: the longer half
- Meanders only add length
Delay
KiCad’s net inspector adds up all copper on the net, so it can differ. Details
STMicroelectronics
Data to strobe | ±1.422 mm |
Address and command to clock | ±3.556 mm |
Strobe to clock | ±12.065 mm |
Pair (P to N) | ±0.127 mm not stated, tool default |
Impedance
DDR memory For DDR3L, DDR4 and LPDDR4 | 55 Ω, 100 Ω differential |
Source: ST AN5724 Rev 4 (2025-12), section 6.3. All ±10%.
Parts: STM32MP25
Source: ST DDR4 length equalization sheet for STM32MP25xxAI, with AN5724 open
Package lengths per ball come with this part, so lengths include the wiring inside the package. AN5724 sets no pair limit: it forbids equalizing inside a pair and takes the mean of N and P as the pair's length, so the tool's default stands there.
Data to strobe | ±1.016 mm |
Address and command to clock | ±1.016 mm |
Strobe to clock | ±14.986 mm |
Pair (P to N) | ±0.127 mm not stated, tool default |
Impedance
DDR memory For DDR3, DDR3L, LPDDR2 and LPDDR3 | 55 Ω, 100 Ω differential |
Source: ST AN5122 Rev 3 (2019-02), section 5.3. All ±10%.
Parts: STM32MP151, STM32MP153, STM32MP157
Source: ST AN5122 Rev 3 (2019-02), STM32MP1 Series DDR memory routing guidelines, sections 6.1 to 6.3 open
The note's windows are one sided: address and command must be 0 to 40 mil shorter than the clock, and the strobe 0 to 590 mil shorter, with the clock the longest trace of all. This tool centers both on the clock, so it checks the size of the difference but not its direction. Like AN5724 it sets no pair limit, taking the mean of N and P instead, so the tool's default stands there. The chip to chip figure is for the two-device fly-by case.
Rockchip
Data to strobe | ±0.635 mm |
Address and command to clock | ±1.016 mm |
Strobe to clock | ±5.080 mm |
Pair (P to N) | ±0.127 mm |
Impedance
DDR memory Address and command may be 40 to 50 ohms on LPDDR5; CKE is 50 ohms on LPDDR4 and LPDDR4X | 40 Ω, 80 to 90 Ω differential |
PCI Express The reference clock is 100 ohms | 85 Ω differential |
USB 2.0 | 90 Ω differential |
Source: RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-7 to 3-11; RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-13 and 3-14; RK3588 Hardware Design Guide V1.0 (2022-01-06), table 3-18. All ±10%.
Parts: RK3588, RK3588S
Source: RK3588 Hardware Design Guide V1.0 (2022-01-06), table 3-7 open
For the 10-layer HDI stackup, where the guide matches by length. WCLK is held to the same limit as DQS. Rockchip strongly recommends its own DDR template.
Data to strobe | ±0.635 mm |
Address and command to clock | ±1.016 mm |
Strobe to clock | ±6.350 mm |
Pair (P to N) | ±0.127 mm |
Impedance
DDR memory Address and command may be 40 to 50 ohms on LPDDR5; CKE is 50 ohms on LPDDR4 and LPDDR4X | 40 Ω, 80 to 90 Ω differential |
PCI Express The reference clock is 100 ohms | 85 Ω differential |
USB 2.0 | 90 Ω differential |
Source: RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-7 to 3-11; RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-13 and 3-14; RK3588 Hardware Design Guide V1.0 (2022-01-06), table 3-18. All ±10%.
Parts: RK3588, RK3588S
Source: RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-8 and 3-9 open
For the 10-layer HDI stackup, where the guide matches by length.
Data to strobe | ±16 ps |
Address and command to clock | ±16 ps |
Strobe to clock | ±40 ps |
Pair (P to N) | ±1 ps |
Impedance
DDR memory Address and command may be 40 to 50 ohms on LPDDR5; CKE is 50 ohms on LPDDR4 and LPDDR4X | 40 Ω, 80 to 90 Ω differential |
PCI Express The reference clock is 100 ohms | 85 Ω differential |
USB 2.0 | 90 Ω differential |
Source: RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-7 to 3-11; RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-13 and 3-14; RK3588 Hardware Design Guide V1.0 (2022-01-06), table 3-18. All ±10%.
Parts: RK3588, RK3588S
Source: RK3588 Hardware Design Guide V1.0 (2022-01-06), tables 3-10 and 3-11 open
For the 8-layer through-hole stackup. The guide gives these as delays, because surface and inner layers differ in speed, so the limits here are in picoseconds.
Data to strobe | ±15.240 mm |
Address and command to clock | ±12.700 mm |
Strobe to clock | ±30.480 mm |
Pair (P to N) | ±0.305 mm |
Impedance
DDR memory ECC control signals are 43 ohms in the region under the chip | 50 Ω, 100 Ω differential |
USB 2.0 | 90 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
PCI Express | 85 Ω differential |
MIPI D-PHY (CSI/DSI) | 100 Ω differential |
SD / eMMC | 50 Ω |
Ethernet RGMII | 50 Ω |
Source: RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 20 to 34; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 1; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 2; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 5 and 6; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 10; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 11 to 13; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 19. All ±10%.
Parts: RK3566, RK3568
Source: RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 33 and 34 open
The guide says DQ and DM need not match DQS, only stay under 600 mil and be as short as possible, so the data limit here is that bound rather than a matching requirement.
Data to strobe | ±15.240 mm |
Address and command to clock | ±15.240 mm |
Strobe to clock | ±38.100 mm |
Pair (P to N) | ±0.305 mm |
Impedance
DDR memory ECC control signals are 43 ohms in the region under the chip | 50 Ω, 100 Ω differential |
USB 2.0 | 90 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
PCI Express | 85 Ω differential |
MIPI D-PHY (CSI/DSI) | 100 Ω differential |
SD / eMMC | 50 Ω |
Ethernet RGMII | 50 Ω |
Source: RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 20 to 34; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 1; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 2; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 5 and 6; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 10; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 11 to 13; RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), table 19. All ±10%.
Parts: RK3566, RK3568
Source: RK3568 High Speed PCB Design Guide V1.0 (2021-04-12), tables 27 to 29 open
Address and command are held to the guide's 600 mil for the controller-to-memory run. The guide holds CSn, CKE and ODT to 30 mil instead, which this tool does not separate, and the branches after a memory device to 20 mil of each other.
Data to strobe | ±5 ps |
Address and command to clock | ±10 ps |
Strobe to clock | ±150 ps |
Pair (P to N) | ±1 ps |
Impedance
DDR memory | 50 Ω, 100 Ω differential |
SD / eMMC | 50 Ω |
PCI Express | 100 Ω differential |
USB 2.0 | 90 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 100 Ω differential |
Source: RK3399 Design Guide V1.0 (2017-04-20), tables 4-1 to 4-8; RK3399 Design Guide V1.0 (2017-04-20), tables 4-9 and 4-17; RK3399 Design Guide V1.0 (2017-04-20), table 4-10; RK3399 Design Guide V1.0 (2017-04-20), table 4-11; RK3399 Design Guide V1.0 (2017-04-20), table 4-12; RK3399 Design Guide V1.0 (2017-04-20), table 4-16. All ±10%.
Parts: RK3399
Source: RK3399 Design Guide V1.0 (2017-04-20), tables 4-5 to 4-8 open
The guide gives these as delays. Its 5 ps applies inside a byte lane; between byte lanes the clock-to-strobe limit of 150 ps governs.
Data to strobe | ±5 ps |
Address and command to clock | ±5 ps |
Strobe to clock | ±150 ps |
Pair (P to N) | ±1 ps |
Impedance
DDR memory | 50 Ω, 100 Ω differential |
SD / eMMC | 50 Ω |
PCI Express | 100 Ω differential |
USB 2.0 | 90 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 100 Ω differential |
Source: RK3399 Design Guide V1.0 (2017-04-20), tables 4-1 to 4-8; RK3399 Design Guide V1.0 (2017-04-20), tables 4-9 and 4-17; RK3399 Design Guide V1.0 (2017-04-20), table 4-10; RK3399 Design Guide V1.0 (2017-04-20), table 4-11; RK3399 Design Guide V1.0 (2017-04-20), table 4-12; RK3399 Design Guide V1.0 (2017-04-20), table 4-16. All ±10%.
Parts: RK3399
Source: RK3399 Design Guide V1.0 (2017-04-20), tables 4-1 to 4-4 open
The guide gives these as delays. Command and control are both held to 5 ps against the clock.
NXP
Data to strobe | ±50 ps |
Address and command to clock | ±50 ps |
Strobe to clock | ±75 ps |
Pair (P to N) | ±1 ps |
Impedance
i.MX 93
DDR memory 85 ohms is for the strobes and the clock | 50 Ω, 85 Ω differential |
Ethernet RGMII | 50 Ω |
Ethernet RMII/MII | 50 Ω |
SD / eMMC | 50 Ω |
USB 2.0 | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 50 Ω, 100 Ω differential |
Differential pairs The guide's figure for differential signals it does not list by name, Ethernet among them | 100 Ω differential |
Source: NXP i.MX 93 Hardware Design Guide Rev. 1 (2023-04-24), table 22. All ±10%.
i.MX 8M Plus
DDR memory 85 ohms is for the strobes and the clock | 50 Ω, 85 Ω differential |
Ethernet RGMII | 50 Ω |
Ethernet RMII/MII | 50 Ω |
SD / eMMC | 50 Ω |
USB 2.0 | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 50 Ω, 100 Ω differential |
Differential pairs The guide's figure for differential signals it does not list by name, Ethernet among them | 100 Ω differential |
PCI Express The reference clock is 100 ohms | 85 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
Source: NXP i.MX 8M Plus Hardware Developer's Guide Rev. 1 (2024-03-26), table 22. All ±10%.
i.MX 8M Nano
No figures from the i.MX 8M Nano guide yet, so the usual ones apply.
Parts: i.MX 93, i.MX 8M Plus, i.MX 8M Nano
Source: NXP i.MX 93 Hardware Design Guide Rev. 1 (2023-04-24), table 16, i.MX 8M Plus Hardware Developer's Guide Rev. 1 (2024-03-26), table 18, and i.MX 8M Nano Hardware Developer's Guide Rev. 1 (2020-11), table 22 open
All three guides hold these limits, at 3733, 4000 and 3200 MT/s. They also ask subgroups of CA to match within 2 ps of each other, and the i.MX 93 holds CS0 and CS1 to 1 ps of the clock, neither of which this tool separates from address and command. The i.MX 93 strobe window is not centered (125 ps short, 75 ps long) and the tighter side is used.
Data to strobe | ±10 ps |
Address and command to clock | ±25 ps |
Strobe to clock | ±85 ps |
Pair (P to N) | ±1 ps |
Impedance
i.MX 8M Mini
DDR memory 85 ohms is for the strobes and the clock | 50 Ω, 85 Ω differential |
Ethernet RGMII | 50 Ω |
Ethernet RMII/MII | 50 Ω |
SD / eMMC | 50 Ω |
USB 2.0 | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 50 Ω, 100 Ω differential |
Differential pairs The guide's figure for differential signals it does not list by name, Ethernet among them | 100 Ω differential |
PCI Express The reference clock is 85 ohms too | 85 Ω differential |
Source: NXP i.MX 8M Mini Hardware Developer's Guide Rev. 1 (2019-08), table 32. All ±10%.
i.MX 8M Quad/Dual
DDR memory 85 ohms is for the strobes and the clock. LPDDR4 DQ and DMI are 42 ohms | 50 Ω, 85 Ω differential |
Ethernet RGMII | 50 Ω |
Ethernet RMII/MII | 50 Ω |
SD / eMMC | 50 Ω |
USB 2.0 | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 50 Ω, 100 Ω differential |
Differential pairs The guide's figure for differential signals it does not list by name, Ethernet among them | 100 Ω differential |
PCI Express The reference clock is 100 ohms | 85 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
Source: NXP i.MX 8MDQLQ Hardware Developer's Guide Rev. 2 (2019-06), table 25. All ±10%.
Parts: i.MX 8M Mini, i.MX 8M Quad, i.MX 8M QuadLite, i.MX 8M Dual
Source: NXP i.MX 8M Mini Hardware Developer's Guide Rev. 1 (2019-08), table 21, and i.MX 8MDQLQ Hardware Developer's Guide Rev. 2 (2019-06), table 16 open
Both guides hold these limits, at 3000 MT/s on the Mini and 3200 on the Quad. They also cap the clock's own flight time, which this tool does not check.
Data to strobe | ±10 ps |
Address and command to clock | ±25 ps |
Strobe to clock | ±1250 ps |
Pair (P to N) | ±1 ps |
Impedance
i.MX 8M Mini
DDR memory 85 ohms is for the strobes and the clock | 50 Ω, 85 Ω differential |
Ethernet RGMII | 50 Ω |
Ethernet RMII/MII | 50 Ω |
SD / eMMC | 50 Ω |
USB 2.0 | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 50 Ω, 100 Ω differential |
Differential pairs The guide's figure for differential signals it does not list by name, Ethernet among them | 100 Ω differential |
PCI Express The reference clock is 85 ohms too | 85 Ω differential |
Source: NXP i.MX 8M Mini Hardware Developer's Guide Rev. 1 (2019-08), table 32. All ±10%.
i.MX 8M Quad/Dual
DDR memory 85 ohms is for the strobes and the clock. LPDDR4 DQ and DMI are 42 ohms | 50 Ω, 85 Ω differential |
Ethernet RGMII | 50 Ω |
Ethernet RMII/MII | 50 Ω |
SD / eMMC | 50 Ω |
USB 2.0 | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 50 Ω, 100 Ω differential |
Differential pairs The guide's figure for differential signals it does not list by name, Ethernet among them | 100 Ω differential |
PCI Express The reference clock is 100 ohms | 85 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
Source: NXP i.MX 8MDQLQ Hardware Developer's Guide Rev. 2 (2019-06), table 25. All ±10%.
Parts: i.MX 8M Mini, i.MX 8M Quad, i.MX 8M QuadLite, i.MX 8M Dual
Source: NXP i.MX 8M Mini Hardware Developer's Guide Rev. 1 (2019-08), table 28, and i.MX 8MDQLQ Hardware Developer's Guide Rev. 2 (2019-06), table 21 open
The guides bound the strobe against the clock at one clock period rather than a window, which is 1250 ps at 1600 MT/s, and a strobe shorter than the clock is allowed.
Data to strobe | ±10 ps |
Address and command to clock | ±25 ps |
Strobe to clock | ±833 ps |
Pair (P to N) | ±1 ps |
Impedance
DDR memory 85 ohms is for the strobes and the clock. LPDDR4 DQ and DMI are 42 ohms | 50 Ω, 85 Ω differential |
Ethernet RGMII | 50 Ω |
Ethernet RMII/MII | 50 Ω |
SD / eMMC | 50 Ω |
USB 2.0 | 90 Ω differential |
MIPI D-PHY (CSI/DSI) | 50 Ω, 100 Ω differential |
Differential pairs The guide's figure for differential signals it does not list by name, Ethernet among them | 100 Ω differential |
PCI Express The reference clock is 100 ohms | 85 Ω differential |
USB 3 SuperSpeed | 90 Ω differential |
Source: NXP i.MX 8MDQLQ Hardware Developer's Guide Rev. 2 (2019-06), table 25. All ±10%.
Parts: i.MX 8M Quad, i.MX 8M QuadLite, i.MX 8M Dual
Source: NXP i.MX 8MDQLQ Hardware Developer's Guide Rev. 2 (2019-06), table 21 open
The strobe is bounded against the clock at one clock period, 833 ps at 2400 MT/s. Not for the i.MX 8M Mini with DDR4: its own guide asks address and command to run 75 to 125 ps shorter than the clock, an offset this tool cannot center.
Data to strobe | ±10 ps |
Address and command to clock | ±10 ps |
Strobe to clock | ±833 ps |
Pair (P to N) | ±1 ps |
Impedance
No figures from the i.MX 8M Nano guide yet, so the usual ones apply.
Parts: i.MX 8M Nano
Source: NXP i.MX 8M Nano Hardware Developer's Guide Rev. 1 (2020-11), table 25 open
The Nano holds address and command to 10 ps of the clock, tighter than the 8M Quad's 25 ps. The strobe is bounded against the clock at one clock period, 833 ps at 2400 MT/s.
Texas Instruments
Data to strobe | ±49 ps |
Address and command to clock | ±312.5 ps |
Strobe to clock | ±3750 ps |
Pair (P to N) | ±0.75 ps |
Impedance
DDR memory | 40 Ω, 80 Ω differential |
Source: TI SPRAD06C (2025-03), table 1-1. All ±10%.
Parts: AM62x, AM62Lx, AM625, AM623
Source: TI AM62x, AM62Lx DDR Board Design and Layout Guidelines SPRAD06C (2025-03), tables 3-6 and 3-7 open
For LPDDR4-1600, the one rate the guide covers. Per-bit deskew in the PHY is why these are loose. TI matches within a byte lane only, and asks the clock to be the longer of the two, by up to three clock periods. The pair limit is the clock pair's 0.75 ps, tighter than the strobe pair's 1.5 ps. Data may run 150 ps longer than its strobe but only 49 ps shorter, and the tighter side is used.
Data to strobe | ±2 ps |
Address and command to clock | ±3 ps |
Strobe to clock | ±12.065 mm not stated, tool default |
Pair (P to N) | ±0.4 ps |
Impedance
DDR memory | 40 Ω, 80 Ω differential |
Source: TI SPRACU1A (2021-06), table 1-1. All ±10%.
Parts: AM64x, AM243x, AM6442, AM2434
Source: TI AM64x\AM243x DDR Board Design and Layout Guidelines SPRACU1A (2021-06), tables 3-6 and 3-7 open
For LPDDR4-1600, the one rate the guide covers. Far tighter than the AM62x, whose PHY deskews per bit. The pair limit is 0.4 ps for both the clock and the strobe. The guide sets no strobe against clock limit at all, matching only within a byte lane, so the tool's default stands there.
Data to strobe | ±0.254 mm |
Address and command to clock | ±0.508 mm |
Strobe to clock | ±12.065 mm not stated, tool default |
Pair (P to N) | ±0.051 mm |
Impedance
AM62x
DDR memory | 40 Ω, 80 Ω differential |
Source: TI SPRAD06C (2025-03), table 1-1. All ±10%.
AM64x/AM243x
DDR memory | 40 Ω, 80 Ω differential |
Source: TI SPRACU1A (2021-06), table 1-1. All ±10%.
Parts: AM62x, AM62Lx, AM625, AM623, AM64x, AM243x, AM6442, AM2434
Source: TI AM62x, AM62Lx DDR Board Design and Layout Guidelines SPRAD06C (2025-03), tables 2-6 and 2-7, and AM64x\AM243x DDR Board Design and Layout Guidelines SPRACU1A (2021-06), tables 2-6 and 2-7 open
Both guides give the same DDR4 tables, for DDR4-1600 only. They give ps as a normalized length, 1 ps to 5 mil of stripline, so these are TI's figures times five: microstrip is meant to be divided by 1.1 first, which this tool does not do. Address and command use the 4 ps total from the processor to each device; each fly-by segment is also held to 3 ps on its own. The pair limit is the strobe pair's 0.4 ps, tighter than the clock pair's 0.8 ps total. The guides set no strobe against clock limit, so the tool's default stands there.
Microchip
Data to strobe | ±2.540 mm |
Address and command to clock | ±5.080 mm |
Strobe to clock | ±10.160 mm |
Pair (P to N) | ±0.508 mm |
Impedance
No figures from the SAMA5D3, ATSAMA5D3 guide yet, so the usual ones apply.
Parts: SAMA5D3, ATSAMA5D3
Source: Microchip SAMA5D3 Layout Recommendations, Atmel-11284B (2016-04-11), section 3.3 open
The note gives these as lengths in mils, as prose rather than a table. The 20 mil pair figure is for both the strobe and the clock.
Data to strobe | ±2.540 mm |
Address and command to clock | ±5.080 mm |
Strobe to clock | ±12.065 mm not stated, tool default |
Pair (P to N) | ±0.508 mm |
Impedance
DDR memory The note says 90 or 100 ohms differential, for the board as a whole | 50 Ω, 90 to 100 Ω differential |
Source: Microchip AN2814 Rev. A (2018-10), section 5.1.2. All ±10%.
Parts: SAMA5D2, ATSAMA5D2
Source: Microchip SAMA5D2 Layout Recommendations, AN2814 Rev. A (2018-10), section 2.3 open
Revision A deleted the strobe against clock bound the earlier revision carried, so the tool's default stands there. It also loosened data to strobe from 50 mil to 100 mil.
Every number is the vendor’s own, for the memory type named, except the few marked as the tool’s default where a guide sets no limit. Where a guide asks for something this tool cannot express, the chip says so.
Analyze a board
Drop all files here at once.
.kicad_pcb
.kicad_pro, for your net classes
.kicad_dru, if the board has one
For example /ddr4/. Detected if empty.
For example U3. Detected if empty.