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BenchPod pin-out

Where everything is on the board, and what each pin does. Both diagrams look down at the pod in the same orientation, so the LA1 corner of the header points at the SMA end in each of them.

J1 — the logic-analyzer header

A 2×10 header carrying the LA channels plus power, ground and CAN. Even pins run down one side and odd pins down the other, with pin 1 (LA1) at the bottom right — the square pad, at the ADC/DAC end of the board. The pod has no role-named pins: there is no pin marked SWCLK, so you choose which channel carries which signal and record that mapping in your test.

BenchPod J1 header pinoutA 2 by 10 header shown with pin 1 at the bottom right, on the ADC and DAC side of the pod. Even pins 2 to 14 run down the left and are LA2, LA4, LA6, LA8, LA10, LA12 and LA14; odd pins 1 to 13 run down the right and are LA1, LA3, LA5, LA7, LA9, LA11 and LA13. Pins 15 and 16 are ground, pin 17 is plus 3.3 volts, pin 18 is plus 1.8 volts, pin 19 is CAN plus and pin 20 is CAN minus. LA1 to LA6 have pull-up resistors, LA7 and LA8 have pull-downs, and LA9 to LA12 have neither. LA13 and LA14 are not exposed by the firmware.pull-upspull-downsCAN−2019CAN++1V81817+3V3GND1615GNDLA141413LA13LA121211LA11LA10109LA9LA887LA7LA665LA5LA443LA3LA221LA1▼ ADC / DAC side of the podpin 1 (LA1) is the square pad — bottom right, at the ADC/DAC endLA1–LA6 pull-ups, LA7/LA8 pull-downs (3.3 V only); LA9–LA12 neitherLA13 / LA14 reach the FPGA but are not exposed by the firmwareJ1, looking down at the pod — LA1 at the bottom right

Eight of the twelve channels carry a fixed bias network, and they do not all pull the same way — LA7 and LA8 pull down. Each is switched in and out individually; all of them are off (high-Z) at boot.

LA channelNetworkValueGood for
LA1, LA2pull-up4.7kOpen-drain buses — an emulated or real I2C bus goes here
LA3, LA4pull-up2.2k
LA5, LA6pull-up10k
LA7, LA8pull-down10kHolding a line low by default — a boot-mode or enable strap
LA9 – LA12none—Anything that must float — nothing biases these

The resistors hang off +3V3 rather than the LA bank rail, so the pod engages them only while the bank is at 3.3 V — at 1.8 V an enable is refused and anything already on is released. In a test, pins.has_pullup(n) and pins.has_pulldown(n) answer this per channel rather than hard-coding it.

Connectors on the board

The same view, zoomed out to the whole pod:

BenchPod connector layoutThe pod seen from above. Along the top edge, left to right: an RJ45 Ethernet jack, the USB connector, and a green 5 volt output screw terminal whose positive pin is on the left and negative on the right. Along the bottom edge, left to right, four SMA connectors: 0 to 3.3 volt DAC, 0 to 5 volt DAC, plus or minus 12 volt DAC, and plus or minus 30 volt ADC. On the right edge near the top are two green screw terminals: the upper one is the 0 to 20 volt output, the lower one is the 5 to 20 volt input; both have ground on their lower pin. On the left edge, in the middle, is the J1 logic-analyzer header, with LA1 at its bottom right corner nearest the SMA end.RJ45USB5V out+−0–20 Voutput+GNDInput5–20 V+GNDJ1 — LA headerLA1 at the bottom-right ↘0–3V3DAC0–5VDAC±12VDAC±30VADCLooking down at the podgreen = screw terminal; every screw terminal has GND on its lower pinthe 5V out terminal is + on the left, − (black) on the right
  • Top edge — the RJ45 jack (wired Ethernet, the pod's primary network interface), the USB connector that carries the console, and a green 5V out screw terminal: positive on the left, negative (the black lead) on the right.
  • Right edge, towards the top — two green screw terminals. The upper one is the 0–20 V output; the one below it is the input, which accepts 5–20 V. Both have GND on their lower pin.
  • Bottom edge — four SMA connectors, left to right: the 0–3V3 DAC, the 0–5V DAC, the ±12V DAC and the ±30V ADC.
  • Left edge, middle — J1, the LA header above, with LA1 at the corner nearest the SMA end.